Manuscript Number : IJSRST229569

Low Power Voltage Level Shifter Employing Power Gating for IOT Applications

Authors(2) :-Aakula Vinod Kumar, T. Sesha Giri

Power management is of increasing concern and challenge to SOC and product designer. Power Gating (PG) is now well understood as a technique for reducing static leakage power when circuits are idle In the IOT applications, Level shifters (LS) are used to transport digital signals from the near-threshold voltage level to the actual supply voltage level when interfacing the near-threshold domain and the nominal voltage domain. The LS should be quick enough to meet needs while keeping transition energy and static power as low as possible in order to reduce overhead. For this, we are proposing the double current limiter level shifter with Power Gating Technique which reduces the power consumption by preventing the supply directly connected to the circuit. At the power supply, two transistors were connected in parallel to obtain the design. Level Shifter that meets the requirements of contemporary IOT applications for power, delay, and voltage level shifting. The proposed Level Shifter was implemented in 45nm technology using Tanner EDA tool.

Authors and Affiliations

Aakula Vinod Kumar
Department of ECE, Shree Institute of Technical Education, Tirupati, Andhra Pradesh, India
T. Sesha Giri
Professor, Department of ECE, Shree Institute of Technical Education, Tirupati, Andhra Pradesh, India

Double Current Limiter, Level Shifter, Power Gating, IOT Applications, Power Consumption.

  1. D. Blaauw et al., IoT design space challenges: Circuits and systems, 2014 Symposium on VLSI Technology: Digest of Technical Papers, 2014, pp. 1-2
  2. R. G. Dreslinski, et al, Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits, in Proceedings of the IEEE, vol. 98, no. 2, pp. 253-266, Feb. 2010.
  3. Jun Zhou et al, An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage, IEEE transactions on circuits and systems, vol. 62, Issue 3, March 2015.
  4. Marco Lanuzza et al, Low-Power Level Shifter for Multi-Supply Voltage Designs, IEEE transactions on circuits and systems, vol. 59, Issue 12, pp.922-926, Dec 2012.
  5. Marco Lanuzza et al, Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs, IEEE transactions on VLSI systems, vol. 23, Issue 2, pp.388-391, Feb 2015.
  6. Srinivasulu Gundala et al, High Speed Energy Efficient Level Shifter for multi Core Processors, International Conference on Circuits, Communication, Control and Computing, Banglore, India, 21-22 November 2014, pp 393-397.
  7. Mahaboob Basha M et al, Design of Ultra-Low-Voltage Energy Efficient Hybrid Full Adder Circuit In: Li J., Sankar A., Beulet P. (eds) VLSI Design: Circuits, Systems and Applications. Lecture Notes in Electrical Engineering, vol 469 Springer, Singapore

Publication Details

Published in : Volume 9 | Issue 5 | September-October 2022
Date of Publication : 2022-10-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 355-360
Manuscript Number : IJSRST229569
Publisher : Technoscience Academy

Print ISSN : 2395-6011, Online ISSN : 2395-602X

Cite This Article :

Aakula Vinod Kumar, T. Sesha Giri, " Low Power Voltage Level Shifter Employing Power Gating for IOT Applications ", International Journal of Scientific Research in Science and Technology(IJSRST), Print ISSN : 2395-6011, Online ISSN : 2395-602X, Volume 9, Issue 5, pp.355-360, September-October-2022.
Journal URL : https://ijsrst.com/IJSRST229569
Citation Detection and Elimination     |      | | BibTeX | RIS | CSV

Article Preview